Several trends presently exist in the semiconductor and electronics industry. One of these trends is that recent generations of portable electronic devices are using more memory than previous generations. This increase in memory allows these new devices to store more data, such as music or images, and also provides the devices with more computational power and speed.
Static random access memory (SRAM) is one type of memory that has increased its density and speed in successive generations, thereby facilitating more functional electronic devices. SRAM is typically arranged as an array of memory cells fabricated in an integrated circuit chip, and includes address decoding circuitry to allow access to each cell for read/write functions. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously.
FIG. 1's SRAM memory cell 100A includes cross-coupled inverters 102, 104 that are configured to store a bit of datum through positive (e.g., reinforcing) feedback, such that the cell 100 can only assume one of two possible states, namely a “one” state or a “zero” state. Pass transistors 108, 110 selectively couple the cross-coupled inverters 102, 104 to a bitline (BL) and a complimentary bitline (bitline bar (BLB)). These bitlines can then communicate the bit of datum to and from the outside world. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
A WRITE of a “zero” to the illustrated cell 100B (FIG. 1B) is achieved by asserting the desired value on the BL and a complement of that value on BLB. While these values are presented on the bitlines, the WL is briefly asserted to enable the pass transistors 108, 110, thereby passing the values to the cross-coupled inverters. Because each inverter inverts (or flips) its input value, the cross-coupled inverters positively reinforce one another, thereby latching the desired data in the cell 100B.
A READ of the illustrated cell 100C (FIG. 1C) is affected by initially precharging both bitlines to a logical high state and then asserting the WL. In this case, one of the transistors of an inverter in the SRAM cell will pull one bitline lower than its precharged value (in FIG. 1C, BL is pulled low). A sense amplifier (not shown) detects the read current or the voltage differential between the bitlines to produce a logical “one” or “zero,” depending on the internally stored state of the SRAM cell.
Because SRAM cells are often arranged in row-column format, the bitlines BL and BLB are typically coupled to multiple pass transistors associated with cells in a column of SRAM cells. Thus, when the bitlines are asserted to read or write to only a single row of cells, the pass transistors of the other unaccessed cells may also be subject to this bitline voltage. To keep the individual cells stable when they are not being accessed, it is desirable to keep the voltage thresholds Vt of the memory cell's transistors sufficiently high. In addition, it is desirable to have the cells provide a high enough read current for the sense amp to quickly sense whether a “one” or “zero” is stored in the cell. This may facilitate fast read times.
Accordingly, it would be desirable to have methods and devices that provide increased read current while keeping Vt, the voltage at which a transistor of the memory cell begins to conduct, sufficiently high; particularly where the transistors may be used in SRAM devices.